1. Field of the Invention
The present invention relates to an integrated circuit device including a circuit for powering down by halting power supply.
2. Description of Related Art
Power saving of integrated circuit devices increases importance with the widespread of equipment such as mobile telephones, which supplies power to integrated circuits from a battery. To save consumption current of the integrated circuits, power supply to semiconductor devices can be suspended in accordance with the operating state of the equipment.
FIG. 6 shows a CMOS tri-state driver embedded in a conventional integrated circuit, and FIG. 7 shows an example of an output circuit using the CMOS tri-state driver of FIG. 6. In FIG. 6, the CMOS tri-state driver 120 consists of a P-channel MOS transistor 121 and an N-channel MOS transistor 122 which are connected in series. In FIG. 7, the output circuit produces an output signal Q that assumes one of the three logical levels xe2x80x9cHxe2x80x9d (high), xe2x80x9cLxe2x80x9d (low) and xe2x80x9cZxe2x80x9d (high-impedance) in response to a drive control signal EN and an output data signal D. The power supply to all the logic gates is denoted by VDD. FIG. 8 is a truth table of the output circuit of FIG. 7.
FIG. 9 shows a CMOS level converter for converting the voltage amplitude of an internal signal of a conventional integrated circuit. It is used for converting the voltage amplitude when the voltage amplitude of an input/output signal of the integrated circuit is greater than that of its internal signal. Using internal signals of a reduced voltage amplitude in the integrated circuit is effective to save its power. As a relevant prior art, a xe2x80x9cStrong ARM processorxe2x80x9d is known which is disclosed on page 121 of xe2x80x9cHOT Chips 8-1996 Symposium Recordxe2x80x9d.
In FIG. 9, DH and DL designate complementary inputs, and QH and QL designate complementary outputs. The xe2x80x9cHxe2x80x9d voltage of the input signals DH and DL is lower than the voltage supplied to P-channel MOS transistors P1 and P2 of the level converter. Circuit constants of the P-channel MOS transistor P1 and N-channel MOS transistor N1 are set in advance such that when the N-channel MOS transistor N1 is brought into conduction, the potential of the output signal QL is sufficiently dropped to such a level that brings the P-channel MOS transistor P2 into conduction.
Likewise, circuit constants of the P-channel MOS transistor P2 and N-channel MOS transistor N2 are set in advance such that when the N-channel MOS transistor N2 is brought into conduction, the potential of the output signal QH is sufficiently dropped to such a level that brings the P-channel MOS transistor P1 into conduction.
When the input signals DH and DL are placed at xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d, respectively, the N-channel MOS transistor N1 is brought into conduction and the N-channel MOS transistor N2 is brought out of conduction. This drops the potential of the output signal QL, and brings the P-channel MOS transistor P2 into conduction, thereby raising the potential of the output signal QH, and bringing the P-channel MOS transistor P1 out of conduction. Thus, the output signal QH becomes xe2x80x9cHxe2x80x9d, and the output signal QL becomes xe2x80x9cLxe2x80x9d. In this case, the potential difference between the output signals QH and QL equals the potential difference between the source terminals of the P-channel MOS transistors and N-channel MOS transistors of the level converter. Thus, the output signals QH and QL can be obtained with a potential difference varying from that between the input signals DH and DL.
FIG. 10 is an example of a conventional output circuit combining the CMOS tri-state driver of FIG. 6 with the CMOS level converter of FIG. 9. The output circuit operates just as that of FIG. 7 except that the voltage amplitude of the drive control signal EN and output data signal D differs from that of the output signal Q. The power to all the logic gates is supplied from an internal power supply with a voltage lower than VDD.
FIG. 11 shows an input/output circuit using the output circuit of FIG. 7. As is well known, a plurality of such input/output circuits are usually connected together to each line of a bus, and are controlled such that only one of them drives the line of the bus at a time. The input/output circuit includes the CMOS tri-state driver 120 consisting of the P-channel MOS transistor 121 and the N-channel MOS transistor 122 which are connected in series; and a controller circuit for controlling the CMOS tri-state driver 120. The input/output circuit places, when the drive control signal EN is xe2x80x9cLxe2x80x9d, its output signal Q at the high-impedance state xe2x80x9cZxe2x80x9d regardless of the level of the output data signal D so that another input/output circuit connected to the same line can drive its output signal Q to xe2x80x9cHxe2x80x9d or xe2x80x9cLxe2x80x9d. In addition, the input/output circuit transfers the level changes of the output signal Q as an input data signal N. The power supply to all the logic gates in the output/input circuit is VDD.
FIG. 12 shows an input/output circuit employing the output circuit as shown in FIG. 9. The input/output circuit operates just as that of FIG. 11 except that the voltage amplitude of the drive control signal EN and output data signal D differs from that of the output signal Q. The power to all the logic gates is supplied from an internal power supply with a voltage lower than VDD.
FIG. 13 shows an example of a computer system configured by applying integrated circuits including the input/output circuits of FIG. 11. In FIG. 13, a CPU and a system control LSI share a memory and bus A, and employ the input/output circuits as shown in FIG. 11. When the data transfer between the CPU and memory is enabled by a control signal B from the system control LSI to the CPU, the output circuits of the system control LSI place the bus A at high-impedance state xe2x80x9cZxe2x80x9d so that the CPU carries out the data transfer with the memory through the bus A. In contrast, when the data transfer between the CPU and memory is disabled by the control signal B from the system control LSI to the CPU, the output circuits of the CPU place the bus A at the high-impedance state xe2x80x9cZxe2x80x9d so that the system control LSI carries out the data transfer with the memory through the bus A.
In the computer system as shown in FIG. 13, the consumption power can be greatly reduced by shutting off the power supply to the CPU, when only the system control LSI and memory must be operated. The conventional computer system, however, has a problem of not being able to achieve sufficient power saving because of a drawback involved in the conventional CMOS tri-state drivers employed by the CPU. This will be described in more detail with reference to FIG. 14 illustrating the P-channel MOS transistor 121 of FIGS. 11 and 12 which has its source and backgate connected together to the power supply VDD and its drain connected to a line of the bus. Shutting off the power supply of the CPU (for powering down) will drop the potential of the source, backgate and drain of the P-channel MOS transistor 121 of the CMOS tri-state driver 120. If the system control LSI supplies the bus A with a signal of logic xe2x80x9cHxe2x80x9d in this case, a forward current will flow through the PN junction between the drain and the backgate of the P-channel MOS transistor 121 of the CMOS tri-state driver 120 as shown in FIG. 14. This is because the power supply to CPU is interrupted during the powerdown, and hence the source, which is connected to the power supply of the CPU, is placed at logic xe2x80x9cLxe2x80x9d. Thus, electric charges are supplied from the output terminal of the system control LSI to the power supply terminal of the CPU, thereby hindering the power saving.
In view of this, a CMOS tri-state driver disclosed in Japanese patent application laid-open No. 8-307238/1996, for example, has an additional circuit for supplying the P-channel MOS transistor with a backgate potential as shown in FIG. 15 to prevent the leakage current from flowing into the CPU even during the power shutdown. Although it can prevent the forward current to flow through the PN junction between the drain and the backgate of the P-channel MOS transistor as shown in FIG. 15, since the gate of the P-channel MOS transistor is not supplied with charges in the powerdown mode, a channel is formed in the P-channel MOS transistor, resulting in a leakage to the power supply terminal of the CPU through the channel. In addition, a problem arises of increasing the number of components per output driver.
In the computer system as shown in FIG. 13, the consumption power can also be greatly reduced by halting only the power supply to the internal circuits of the CPU, when it is necessary to operate only the system control LSI and memory but not the CPU. In this case, the output of the CMOS tri-state driver of FIG. 10 must be placed at xe2x80x9cZxe2x80x9d by supplying xe2x80x9cHxe2x80x9d to the gate of the P-channel MOS transistor, and xe2x80x9cLxe2x80x9d to the gate of the N-channel MOS transistor. However, since the power supply is halted to the internal circuit of the CPU which delivers the complementary signals to the pair of the input terminals of the CMOS level converters of FIG. 10, the gate of the P-channel MOS transistor 121 is not supplied with the xe2x80x9cHxe2x80x9d voltage, making it impossible to prevent the leakage current from flowing through the channel to the power supply terminal of the CPU.
FIG. 16 shows a CMOS tri-state driver disclosed in Japanese patent application laid-open No. 9-64718/1997, and FIG. 17 shows a CMOS tri-state driver disclosed in U.S. Pat. No. 4,963,766. To avoid leakage due to a high voltage applied to the output terminal of the CMOS tri-state driver from the output terminal of another driver, the CMOS tri-state driver not only supplies a high voltage to the backgate of the P-channel MOS transistor QP1 or QP42 of FIGS. 16 and 17, but also includes a circuit for raising, through the P-channel MOS transistor QP2 or QP41, the gate voltage of the P-channel MOS transistor QP1 or QP42 in response to the high voltage applied to the output terminal to bring the P-channel MOS transistor QP1 or QP42 out of conduction. Each of the CMOS tri-state drivers, however, has a problem in that the gate of the P-channel MOS transistor QP1 or QP42 is supplied with electric charges through the P-channel MOS transistor QP2 or QP41 connected across the output terminal and the gate, and that this provides a delay which causes a transient leakage current to flow when the voltage applied to the output terminal sharply rises.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide an integrated circuit device capable of effectively shutting off the power supply in the powerdown mode by eliminating the leakage.
According to a first aspect of the present invention, there is provided an integrated circuit device comprising:
a first power supply terminal to which a first fixed potential is supplied; a second power supply terminal to which a second fixed potential is supplied; a third power supply terminal to which a third fixed potential that can be powered down is supplied; an output terminal; a first conductivity type MOS transistor having its source connected to the third power supply terminal, its backgate connected to the second power supply terminal, and its drain connected to the output terminal, the source and backgate being electrically isolated; a second conductivity type MOS transistor having its drain connected to the output terminal, and its backgate and source connected to the first power supply terminal; a potential difference detector connected to the second power supply terminal and the third power supply terminal for detecting a potential difference between them; and a gate potential controller connected to the potential difference detector for controlling a potential of the gate of the first conductivity type MOS transistor in response to an output of the potential difference detector.
Here, the gate potential controller may control a potential of a gate of the second conductivity type MOS transistor in response to the output of the potential difference detector.
According to a second aspect of the present invention, there is provided an integrated circuit device comprising:
a first power supply terminal to which a first fixed potential is supplied; a second power supply terminal to which a second fixed potential is supplied; a third power supply terminal to which a third fixed potential that can be powered down is supplied; an output terminal; a first conductivity type MOS transistor having its source and backgate connected to the second power supply terminal, and its drain connected to the output terminal; a second conductivity type MOS transistor having its drain connected to the output terminal, and its backgate and source connected to the first power supply terminal; a potential difference detector connected to the second power supply terminal and the third power supply terminal for detecting a potential difference between them; and a CMOS level converter for converting outputs of the potential difference detector, and for supplying a converted signal to at least one of a gate of the first conductivity type MOS transistor and a gate of the second conductivity type MOS transistor.
Here, the CMOS level converter may supply, when the potential difference detector detects the potential difference between the second power supply terminal and the third power supply terminal, the gate of the first conductivity type MOS transistor with a potential equal to the potential of the second power supply terminal, and the gate of the second conductivity type MOS transistor with a potential equal to the potential of the first power supply terminal.
The CMOS level converter may comprises: a first power supply terminal to which a first fixed potential is supplied; a second power supply terminal to which a second fixed potential is supplied; a first data input terminal; a second data input terminal; a first output terminal; a second output terminal; a first mode control input terminal; a second mode control input terminal; a first first conductivity type MOS transistor having its source connected to the second power supply terminal, its drain connected to the first output terminal, and its gate connected to the first mode control input terminal; a second first conductivity type MOS transistor having its source connected to the second power supply terminal; its drain connected to the first output terminal, and its gate connected to the second output terminal; a third first conductivity type MOS transistor having its source connected to the second power supply terminal, its drain connected to the second output terminal and its gate connected to the first output terminal; a first second conductivity type MOS transistor having its drain connected to the first output terminal, and its gate connected to the first mode control input terminal; a second second conductivity type MOS transistor having its source connected to the first power supply terminal, its drain connected to a source of the first second conductivity type MOS transistor, and its gate connected to the first data input terminal; a third second conductivity type MOS transistor having its source connected to the first power supply terminal, its drain connected to the second output terminal, and its gate connected to the second mode control input terminal; and a fourth second conductivity type MOS transistor having its source connected to the first power supply terminal, its drain connected to the second output terminal, and its gate connected to the second data input terminal, wherein the first mode control input terminal and the second mode control input terminal may be connected to the potential difference detector, and the first output terminal may be connected to the gate of the first conductivity type MOS transistor.
According to a third aspect of the present invention, there is provided an integrated circuit device comprising:
a first power supply terminal to which a first fixed potential is supplied; a second power supply terminal to which a second fixed potential is supplied; a tri-state driver including a first conductivity type MOS transistor that has a source and a backgate which are isolated from each other and has the-backgate connected to the second power supply terminal, and a second conductivity type MOS transistor that has its drain connected to a drain of the first conductivity type MOS transistor and its source connected to the first power supply terminal; a switching circuit for connecting or disconnecting the source of the first conductivity type MOS transistor with the second power supply terminal; a gate potential controller for controlling a potential of a gate of the first conductivity type MOS transistor; and a power supply controller for controlling the switching circuit and the gate potential controller, wherein the integrated circuit device is partitioned into a first block including the tri-state driver, and a second block including the power supply controller, and wherein the switching circuit disconnects, when the power supply controller powers down the first block, the source of the first conductivity type MOS transistor from the second power supply terminal, and the gate potential controller supplies the gate of the second conductivity type MOS transistor with a potential equal to the potential of the second power supply terminal.
According to a fourth aspect of the present invention, there is provided a CMOS level converter for converting an amplitude potential of a signal, the CMOS level converter comprising:
a first power supply terminal to which a first fixed potential is supplied; a second power supply terminal to which a second fixed potential is supplied; a first data input terminal; a second data input terminal; a first output terminal; a second output terminal; a first mode control input terminal; a second mode control input terminal; a first first conductivity type MOS transistor having its source connected to the second power supply terminal, its drain connected to the first output terminal, and its gate connected to the first mode control input terminal; a second first conductivity type MOS transistor having its source connected to the second power supply terminal; its drain connected to the first output terminal, and its gate connected to the second output terminal; a third first conductivity type MOS transistor having its source connected to the second power supply terminal, its drain connected to the second output terminal and its gate connected to the first output terminal; a first second conductivity type MOS transistor having its drain connected to the first output terminal, and its gate connected to the first mode control input terminal; a second second conductivity type MOS transistor having its source connected to the first power supply terminal, its drain connected to a source of the first second conductivity type MOS transistor, and its gate connected to the first data input terminal; a third second conductivity type MOS transistor having its source connected to the first power supply terminal, its drain connected to the second output terminal, and its gate connected to the second mode control input terminal; and a fourth second conductivity type MOS transistor having its source connected to the first power supply terminal, its drain connected to the second output terminal, and its gate connected to the second data input terminal.
Here, a potential of a signal supplied to the first data input terminal and the second data input terminal may differ from a potential difference between the first power supply terminal and the second power supply terminal, and a potential of a signal supplied to the first mode control input terminal and the second mode control input terminal may equal the potential difference between the first power supply terminal and the second power supply terminal.